This invention relates to a digital electronic circuit which generates a clock signal. More specifically, the present invention relates to a clock generator in which the frequency of the output clock signal is externally programmable. Further, the present invention relates to a frequency programmable clock generator in which the duty cycle of the output clock signal remains constant regardless of the clock signal's frequency.
Many frequency and clock synthesis circuits require a clock signal which varies in accordance with an externally applied rate signal. Many applications additionally require a predetermined, constant duty cycle. For example, many applications prefer a fifty percent duty cycle clock signal because the conversion of the clock signal into a sine wave then requires a minimum amount of filtering. However, the generation of a clock signal which varies in frequency yet exhibits a known, constant duty cycle requires special circuitry.
One prior art circuit which generates a frequency programmable, constant duty cycle clock signal uses a counter and a master clock signal. The master clock signal is doubled in frequency and the doubled frequency clock signal is applied to the counter. The counter may be loaded with different values to achieve the frequency programmability. An output from the counter is then divided by 2 to provide an output clock signal which exhibits a constant duty cycle.
However, this and other similar prior art circuits will not work in certain high frequency applications where the master clock signal, without doubling, oscillates at a frequency which approaches the upper frequency limits of the counter. In this situation, a doubling of the master clock signal produces a signal which is too fast for proper operation of the counter.